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document id# 081132 date: nov 16, 2006 rev: d version: 1 distribution: public document ? le5711 dual subscriber li ne interface circuit ve580 series applications ? ideal for low cost, high performance linecard applications (co, dlc) ? meets requirements for countries such as: china, korea, japan, taiwan, and australia ? fulfills the following china specifications: gf002- 9002.1 features ? dual-channel slic device with small footprint ? on-chip thermal management (tmg) feature in normal and reverse polarity ? control states: active (normal and reverse polarity), standby, and disconnect ? on-hook transmission ? low standby power ? ?39 to ?58 v battery operation ? two-wire impedance set by single external impedance ? device level thermal shutdown ? set on-chip constant-current feed ? programmable ring-trip detect threshold ? only +5 v and battery supply required ordering information 1. the green package meets rohs directive 2002/95/ec of the european council to minimize the environmental impact of electrical equipment. 2. for delivery using a tape and reel packing system, add a "t" suffix to the opn (ordering part number) when placing an order. device package 1 packing 2 LE57D111DJC 32-pin plcc (green), 50 db reverse polarity tube le57d111btc 44-pin etqfp (green), 50 db reverse polarity tray description the innovative le5711 dual-channel slic device is designed for high-density pots applications requiring a small footprint slic device with significant power savings. by combining the line interface of two channels into one slic device, the le5711 device enables the design of a low cost, high performance, and fully programmable line interface for multiple country applications worldwide. the on-chip thermal management (tmg) feature allows for significantly reduced power dissipation on the device. the le5711 device is offered in space-saving package types, 44-pin etqfp and 32-pin plcc. the small footprint of the slic device allows designers to save board space, increasing the dens ity of lines on the board. the le5711 device is also designed to significantly reduce the number of external components required for linecard design. legerity offers a range of compatible codec/filters that perform the codec function in a line card. in particular the legerity qlslac? device, another member of the ve580 series, combined with the le5711 device provides a programmable line circuit that can be conf igured for varying requirements. related literature ? 080753 le58ql02/021/031 qlslac ? data sheet ? 080754 le58ql061/063 qlslac ? data sheet ? 080748 le5711 evaluation board user?s guide block diagram bgnd 1 a 2 (tip) hp 2 b 2 (ring) vtx 2 rsn 2 ch2 2-w interface ch1 2-w interface ch2 input decoder and control common bias off-hook detector ch2 power feed controller ch2 ring trip detector ch2 ring trip detector ch1 power feed controller ch1 off-hook detector ch1 signal transmission ch2 signal transmission ch1 ch1 input decoder and control c2 2 c1 2 det 2 cas ire f det 1 c2 1 c1 1 a 1 (tip) hp 1 b 1 (ring ) vtx 1 rsn 1 bgnd 2 vbat cdc 2 db 2 dac db 1 cdc 1 vcc a gnd/ dgnd tmg 2 tmg 1
2 le5711 ve580 series data sheet table of contents applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 related literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 block descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 two-wire interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 signal transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 power feed controller and common bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 input decoder and control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 off-hook detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 ring-trip detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 transmission performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 crosstalk between channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 longitudinal capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 insertion loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 line characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 power supply rejection ratio at the two-wire interface, active normal state . . . . . . . . . . . . . . .8 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 supply currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 rfi rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 logic output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 ring-trip detector input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 loop detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 slic device decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 user-programmable components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 dc feed characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 application circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 line card parts list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 physical dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 32-pin plcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 revision a1 to b1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 revision b1 to c1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 revision c1 to d1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
le5711 ve580 series data sheet 3 product description the le5711 device is designed for long loop high-density pots ap plications requiring a low power, small footprint slic. the le5711 device increases linecard density by in tegrating two slic devices into a single 32 pin package. this reduction in board space allows for higher density linecard, which allows for am ortizing common hardware across more channels. the le5711 device gives linecard designers a simple c ontrol interface that supports four st ates: active, reverse polarity, standby, and disconnect (ringing). the le5711 device is low cost and high performance, providing key featur es required for pots markets requiring only loop start. the device includes a the rmal management resistor for reducing power dissipation. block descriptions two-wire interface the two-wire interfaces provide dc current and send voice si gnals to a telephone apparatus connected to the linecard with a two-wire line. the two-wire interface also receives the returning voice signals from the telephone transmitter. signal transmission the rsn input current controls the receive current sent to the two-wire interface. the ac line voltage is sensed by a different ial amplifier between the a i (tip) and hp i leads.* the output of this amplifier is equal to the ac metallic components of the line voltages and is output at vtx i . the transmission circuit also contains a longit udinal feedback circuit to shunt longitudinal signals to a dc bias voltage. the longitudinal feedback does not affect metallic signals. *note: "i" denotes channel number power feed contro ller and common bias the power feed controllers have three sections: (1) the battery feed circuit, (2) the reverse po larity circuit, and (3) the com mon bias circuit. the battery feed circuit regulates the amount of dc current and voltage supplied to the telephone over a wide ran ge of loop resistance. the reverse polarity circ uit provides the capability to reverse the loop current for pay telephone key pad disable and other applications. the bias ci rcuit provides a filtered refer ence voltage, which is offset from the subscriber line voltag e, and a signal which sets the current limit. input decoder and control the input decoder a nd control block provides a means for a microprocessor or slac ic to cont rol such system states as active, standby, disconnect (ringing), and reverse polarity. the input dec oder and control block has ttl-compatible inputs, which set the operating states of the slic device. it also provides the supervision signal sent back to the controller. off-hook detector the most important loop monitoring function is off-hook detection. loop current is programmed for both channels by a single resistor. loop detect threshold is typically 1/3 of the progra mmed loop current in the active and reverse polarity states. ring-trip detector in the disconnect state, the ring-t rip detector is active. while the db i pin is more negative than the dac pin, the det pin will be high to indicate on hook. when an off hook condition occurs, the db i pin becomes more positive than the dac pin, and the det pin will go low to indicate off hook during ringing (ring-trip ) has been detected. the system implements the ringing state usin g external control of a ring relay in combination with the disconnect slic state, which enables the ring-trip detector.
4 le5711 ve580 series data sheet connection diagrams note: 1. pin 1 is marked for orientation. 2. nc = no connect 3. the exposed heat sink pad on the bottom of the etqfp package is connected to the battery suppl y (vbat pin). do not connect to gnd. bgnd 1 b 1 (ring) a 1 (tip) db 1 dac vbat db 2 a 2 (tip) b 2 (ring) rsn 2 vtx 2 rsvd 2 hp 2 tmg 2 bgnd 2 cdc 2 4321323130 14 15 16 17 18 19 20 7 9 8 11 10 12 13 6 5 27 25 26 23 24 22 21 28 29 32-pin plcc cdc 1 rsn 1 vtx 1 rsvd 1 hp 1 tmg 1 det 1 c2 1 c1 1 agnd/ dgnd vcc cas iref c1 2 c2 2 det 2 44-pin etqfp 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 44 43 42 41 40 39 38 37 36 35 34 5 6 7 8 9 10 11 4 3 2 1 a 1 (tip) b 1 (ring) bgnd 1 db 1 dac nc vbat db 2 a 2 (tip) b 2 (ring) bgnd 2 nc c1 1 c2 1 agnd/dgnd vcc nc cas iref c1 2 c2 2 rsn 2 nc cdc 2 nc vtx 2 nc nc rsvd 2 nc hp 2 tmg 2 rsn 1 cdc 1 nc vtx 1 nc nc rsvd 1 nc hp 1 tmg 1 det 1 det 2 exposed pad
le5711 ve580 series data sheet 5 pin descriptions pin name type description a 1 (tip) output output of a (tip) power amplifier of channel 1. a 2 (tip) output output of a (tip) power amplifier of channel 2. agnd/dgnd ground analog and digital ground. b 1 (ring) output output of b (ring) power amplifier of channel 1. b 2 (ring) output output of b (ring) power amplifier of channel 2. bgnd 1 ground battery (power) ground of channel 1 bgnd 2 ground battery (power) ground of channel 2. c1 1 input state decoder inputs of channel 1. c2 1 input c1 2 input state decoder inputs of channel 2. c2 2 input cas capacitor pin for capacitor to filter refere nce voltage when operating in anti-saturation region. cdc 1 capacitor dc feed filter capacitor of channel 1. cdc 2 capacitor dc feed filter capacitor of channel 2. rsvd 1 input reserved. connect to v cc . rsvd 2 input reserved. connect to v cc . dac input ring-trip negative of both channels. negative input to ring-trip comparator. db 1 input ring-trip positive of channel 1. posi tive input to ring-trip comparator. db 2 input ring-trip positive of channel 2. posi tive input to ring-trip comparator. det 1 output switch-hook/ring-trip detector output of channel 1. logic low indicates that a detector is tripped. det 2 output switch-hook/ring-trip detector output of channel 2. logic low indicates that a detector is tripped. hp 1 capacitor connect high-pass filter capacitor from hp 1 to b 1 (ring). hp 2 capacitor connect high-pass filter capacitor from hp 2 to b 2 (ring). iref resistor connection for reference resistor that programs loop detector threshold and dc feed current of both channels. nc ? no connect. this pin is not internally connected. rsn 1 input receive summing node of channel 1. in the active and polarity reversed states, the current (both ac and dc) between a 1 (tip) and b 1 (ring) is equal to 500 times the current into this pin. the networks that program receive gain and two-wire impedance of channel 1 connect to this node. rsn 2 input receive summing node of channel 2. in the active and polarity reversed states, the current (both ac and dc) between a 2 (tip) and b 2 (ring) is equal to 500 times the current into this pin. the networks that program receive gain and two-wire impedance of channel 2 connect to this node. tmg 1 output thermal management of channel 1. exte rnal resistor connects from tmg 1 to vbat to offload power from the slic device. tmg 2 output thermal management of channel 2. external resistor connects from tmg2 to vbat to offload power from the slic device. vbat battery battery supply and connection to substrate. vcc power +5 v power supply. vtx 1 output transmit audio signal of channel 1. this output is a scaled version of the a and b metallic voltage. vtx also sources the two-wi re input impedance programming network. vtx 2 output transmit audio signal of channel 2. this output is a scaled version of the a and b metallic voltage. vtx 2 also sources the two-wire input impedance programming network. exposed pad battery the exposed thermal management pad must be in thermal contact with an exposed copper plate with an electrical potent ial of battery supply (vbat pin).
6 le5711 ve580 series data sheet electrical characteristics absolute maximum ratings stresses greater than those listed under absolute maximum ratings can cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute ma ximum ratings for extended periods can affect device reliability notes: 1. thermal limiting circuitry on the chip wi ll shut down the circuit at a junction temperature of about 165oc. continuous operat ion above 145oc junction temperature may degrade device reliability. 2. the thermal performance of a thermally enhanced package is assur ed through optimized printed circuit board layout. refer to t he thermal management for the le5711 and le5712 dual slic devices application note for details. package assembly the green package devices are assembled with enhanced, environ mental compatible lead-free, halogen-free, and antimony-free materials. the leads possess a matte-tin plating which is comp atible with conventional board a ssembly processes or newer lead- free board assembly processes. the peak soldering temperature should not exceed 245c during printed circuit board assembly. refer to ipc/jedec j-std-020b table 5-2 for the recommended solder reflow temperature profile. operating ranges legerity guarantees the performance of this device over commercial (0 to 70o c) and industrial (-40 to 85oc) temperature ranges by conducting electrical characterization over each range and by conducting a production test with single insertion coupled to periodic sampling. these characterization and test procedures comply with secti on 4.6.2 of bellcore gr-357-core component reliability assurance requirements for telecommunications equipment. storage temperature ?55 to +150o c v cc with respect to agnd ?0.4 to +7.0 v v bat with respect to agnd +0.4 to ?61v bgnd 1 , bgnd 2 with respect to agnd +3 to ?3 v a 1 (tip), a 2 (tip), b 1 (ring), b 2 (ring) with respect to bgnd: continuous v bat to + 1 v 10 ms (f = 0.1 hz) ?70 to +5 v 1 s (f = 0.1 hz) ?80 to +8 v 250 ns (f = 0.1 hz) ?90 to +12 v current from a 1 (tip), a 2 (tip), b 1 (ring), b 2 (ring) 150 ma db 1 , db 2 , and dac inputs: voltage on ring-trip inputs v bat to 0 v current into ring-trip inputs 10 ma c1 1 , c2 1 , c1 2 , c2 2 input voltage ?0.4 to v cc + 0.4 v maximum power dissipation, continuous: t a = 70o c, no heat sink in 32-pin plcc package 1.7 w in 44-pin etqfp (see note 1) thermal data (junction to ambient): ja in 32-pin plcc package 43oc/w typ in 44-pin etqfp package (see note 2) thermal data (junction to case): jc in 32-pin plcc package 16oc/w typ in 44-pin etqfp package (see note 2) esd immunity (human body model) jesd22 class 1c compliant
le5711 ve580 series data sheet 7 note: the operating ranges define those limits between which the dev ice operates and is guaranteed under the noted test conditions. specifications transmission performance crosstalk between channels longitudinal capability (see figure 4 , on page 13 .) insertion loss (see figure 2 and figure 3 , on page 12 .) ambient temperature ? 40 to 85c v cc 4.75 to 5.25 v v bat ?39 to ?58 v db1, db2, and dac v bat to ?2 v agnd 0 v bgnd1, bgnd2 with respect to agnd ?100 to + 100 mv load resistance on vtx to ground 20 k ? minimum description test conditions (see note 1) min typ max unit note 2-wire return loss 200 hz to 3.4 khz (see figure 5 )26 db3, 5 analog output (vtx) impedance 3 20 ? 3 analog (vtx) output offset voltage ?50 +50 mv overload level, 2-wire active or reverse polarity state 2.5 vpk 2a overload level on hook 1.1 2b thd (total harmonic distortion) 0 dbm ?64 ?50 db 4 +7 dbm ?55 ?40 thd, on hook 0dbm ?36 description test conditions (see note 1) min typ max unit note crosstalk coupling loss f = 200 hz to 3.4 khz 80 db 3 description test conditions (see note 1) min typ max unit note longitudinal to metallic l-t, l-4 balance 200 hz to 3.4 khz, 0o c to +70o c 50 db 3 longitudinal signal generation 4-l 200 hz to 3.4 khz 40 longitudinal current per pin (a or b) active state (off hook) 8.5 20 marms 6 longitudinal impedance at a or b 0 to 100 hz 25 ?/ pin idle channel noise c-message, r l = 600 ? 712dbrnc3 psophometric, 600 ? ?83 ?78 dbmp description test conditions (see note 1) min typ max unit note gain accuracy, 4-to-2-wire 0 dbm, 1 khz ?0.20 0 +0.20 db gain accuracy, 2-to-4-wire and 4-to-4-wire 0 dbm, 1 khz ?9.74 ?9.54 ?9.34 gain accuracy, 4-to-2-wire on hook ?0.35 +0.35 gain accuracy over frequency 300 to 3.4 khz relative to 1 khz ?0.15 +0.15 gain tracking +3 dbm to ?55 dbm relative to 0 dbm ?0.15 +0.15 3 gain tracking, on hook 0 dbm to ?37 dbm +3 dbm to 0 dbm ?0.15 ?0.35 +0.15 +0.35
8 le5711 ve580 series data sheet line characteristics power supply rejection ratio at the tw o-wire interface, active normal state power dissipation supply currents rfi rejection (see figure 6 , on page 13 .) logic inputs (applies to c1 1 , c1 2 , c2 1 , and c2 2 .) description test conditions (see note 1) min typ max unit note i l , short loops, active state 26.4 30 33.6 ma i l , long loops, active state r ldc = 1930 ? , bat = ?42.75 v, t a = 25c 18 19 i l , accuracy, standby state 0.7i l i l 1.3i l i l , loop current, disconnect state r l = 0 100 a vab, open circuit voltage v bat = ?48 v +38.3 +40.3 v description test conditions (see note 1) min typ max unit note v cc 50 hz to 3.4 khz v ripple = 100 mv rms 30 40 db 4 v bat 50 hz to 3.4 khz v ripple = 500 mv pp 28 50 description test conditions (see note 1) min typ max unit note on hook, both channels, standby state 40 100 mw on hook, both channels, active state 380 540 off hook, both channels, active state r l = 300 ? , r tmg = 1600 ? 1400 1700 one channel, active state one channel, standby state r l = 300 ? , r tmg = 1600 ? 720 1050 description test conditions (see note 1) min typ max unit note i cc , on-hook v cc supply current both channels, standby state 2.5 4.0 ma both channels, active state, bat = ?48 v 9.0 12.0 i bat , on-hook v bat supply current both channels, standby state 0.5 1.5 both channels, active state, bat = ?48 v 6.5 8.5 description test conditions min typ max unit note vtx1 or vtx2 f = .01 to 100 mhz hf gen output = 1.5 vrms c axi = c bxi = 33 nf 1 mvrms 3 c axi = c bxi = 2.2 nf 3 description test conditions min typ max unit note v ih , input high voltage 2.0 v v il , input low voltage 0.8 i ih , input high current ?75 40 a i il , input low current ?400 i l vbat 3v ? r l 3.2 k + () -------------------------------- ?? ?? t a 25 c = , =
le5711 ve580 series data sheet 9 logic output (applies to det1 and det2 .) ring-trip detector input (applies to dac, db1, and db2.) loop detector notes: 1. unless otherwise noted, the test conditions are set up by the le5711 device test circuit as illustrated in figure 7 , on page 14 . 2. a. overload level is defined as thd = 1%. b. overload level is defined when thd = 1.5%. 3. not tested in production. this parameter is guarant eed by characterization or correlation to other tests. 4. this parameter is tested at 1 khz in production. perf ormance at other frequencies is guaranteed by characterization. 5. group delay can be greatly reduced by using a z t network such as that shown in figure 5 . the network reduces the group delay to less than 2 s and increases 2wrl. the effect of group delay on lineca rd performance also may be com pensated by synthesizing complex impedance with the qlslac? device. 6. minimum current level guaranteed not to cause a false loop detect. slic device decoding (for i, channel = 1 or 2) description test conditions (see note 1) min typ max unit note v ol , output low voltage i out = 0.3 ma 0.40 v v oh , output high voltage i out = ?0.1 ma 2.4 description test conditions (see note 1) min typ max unit note bias current ?500 ?50 na common mode range v bat + 1 ? 2v description test conditions (see note 1) min typ max unit note off-hook threshold active 9 11 ma on-hook threshold active 8.5 10.5 off-hook threshold standby 4 6 on-hook threshold standby 3.8 5.8 hysteresis 0 2 state c2 i c1 i two-wire status detx output 0 0 0 disconnect ring-trip detector 1 0 1 active loop detector 211 polarity reversed (le57d111 devices only) loop detector 3 1 0 standby loop detector
10 le5711 ve580 series data sheet user-programmable components note: * "i" denotes channel number equation description z ti * is connected between the vtx and rsn pins. the fuse resistors are r f , and z 2win is the desired 2-wire ac input impedance. when computing z ti , the internal current amplifier pole and any external stray capacitance between vtx and rsn must be taken into account. z rxi * is connected from vrx to rsn. z ti is defined above, and g 42l is the desired receive gain. i loop is the desired loop current in the constant-current region. loop detect threshold is typically 1/3 of programmed loop current. c cas is the regulator filter capacitor and f c is the desired filter cut-off frequency. standby loop current (resistive region). thermal management equations (active, and reverse polarity states for one channel) r tmg is connected from tmg to vbat and limits power within the slic device in active and off-hook states. power dissipated in the tmg resistor, r tmg , during active and off-hook states. power dissipated per channel in the slic device while in active state. z ti 166.7 z 2win 2r f ? ( ) = z rxi z l g 42l ------------ - ? 500z t z t 166.7 z l 2r f + () + --------------------------------------------------------- = r ref 450 i loop --------------- = c dc 1.5 f = c cas 1 170 k ? 2 f c ? ? ------------------------------------------ - = i standby v bat 3v ? 3200 ? r l + --------------------------------- = r tmg v batmax 6 ? vi lmin 2r f r lmin + () ? i lmin ---------------------------------------------------------------------------------------------------- - 40 ? ? p rtmg v bat 6v ? i l ? r l 2r f + () [] ? () 2 r tmg 40 ? + () 2 -------------------------------------------------------------------------------------------- r tmg ? = p slic v bat i l p rtmg ? r l i l () 2 0.12 w + ? ? =
le5711 ve580 series data sheet 11 dc feed characteristics load line (typical) vbat = -48v vbat = -38v vbat = -42v 1 2b 3a 3b on-hook off-hook 2a switch-hook threshold: i swth 150 r ref -------------- = r ref 15 k = regions: 1. constant current region: 2a. battery-independent an ti-sat (off-hook): 2b. battery-independent anti-sat (on-hook): 3a. battery tracking anti-sat (off-hook): 3b. battery tracking anti-sat (on-hook): v ab1 i l r l ' 450 () r ref -------------- r l ' where r l ' r l 2r f + = , = = v ab2a 43.6 vi l 303 ? ? = v ab2b v ab2a 3.5 v ? = v ab3a v bat 1.8 vi l 111 ? ? ? = v ab3b v ab3a 0.33 v bat 10.8 + ? ? =
12 le5711 ve580 series data sheet figure 1. feed programming test circuits figure 2. two-to-four wire insertion loss figure 3. four-to-two wire insertion loss and balance return signals r l a (tip) b (ring) iref cdc slic a b i l c dc r ref slic vtx 1 agnd rsn 1 v ab r t r rx i l2-4 = 20 log(v tx / v ab ) r l 2 r l 2 v l vtx 2 rsn 2 a 1 , a 2 (tip) b 1 , b 2 (ring) slic agnd v ab r t r rx i l4-2 = 20 log(v ab / v rx ) brs = 20 log(v tx / v rx ) v rx r l a 1 , a 2 (tip) b 1 , b 2 (ring) vtx 1 vtx 2 rsn 1 rsn 2
le5711 ve580 series data sheet 13 figure 4. longitudinal balance figure 5. two-wire return loss test circuit figure 6. rfi test circuit slic agnd v ab r t r rx l-t long. bal. = 20 log(v ab / v l ) v rx r l 2 r l 2 v l v l s1 1 c r l << s2 l -4 long. bal. = 20 log(3v tx / v l ) s2 open, s1 closed s2 closed, s1open 4-l long. sig. gen. = 20 log(v l / v rx ) c a 1 , a 2 (tip) b 1 , b 2 (ring) vtx 1 vtx 2 rsn 1 rsn 2 return loss = ?20 log (2v m / v s ) z d : the desired impedance; eg., the characteristic impedance of the line slic agnd r rx = 124 k c t = 120 p f r ta r tb v m v s r r z d = 600 ? z in = 600 ? a 1 , a 2 (tip) b 1 , b 2 (ring) vtx 1 vtx 2 rsn 1 rsn 2 r t 2 r t 2 hf gen l 1 l 2 200 ? 200 ? c 1 c 2 50 ? 50 ? rf 1 rf 2 c ax c bx slic under test 80% amplitude modulated modulation frequency = 1 khz 50 ? vtx 1 vtx 2 a 1 , a 2 (tip) b 1 , b 2 (ring)
14 le5711 ve580 series data sheet figure 7. le5711 test circuit hp 1 b 1 (ring) tmg 1 vbat tmg 2 db 2 dac a 2 (tip) hp 2 b 2 (ring) det 1 c1 1 c2 1 iref cas vtx 2 rsn 2 cdc 2 det 2 c1 2 c2 2 r ing 1 c hp1 c bx1 db 2 dac c ax2 tip 2 c hp2 r ing 2 c bx2 r ref c cas vtx 2 vrx 2 r rx2 r t2 c dc2 ch1 ch2 le5711 det 2 c1 2 c2 2 det 1 c1 1 c2 1 100 nf 2.2 nf r tmg1 r tmg2 bat d vbh 1600 ? 1600 ? 2.2 nf 100 nf 2.2 nf 15 k ? 0.33 f 100 k ? 150 k ? r l , r lac = 600 ? i loop = 30 ma bat = - 52 v 1.5 f vtx 1 rsn 1 vrx 1 vtx 1 r t1 r rx1 100 k ? 150 k ? cdc 1 c dc1 1.5 f db 1 db 1 a 1 (tip) tip 1 c ax 1 2.2 nf bgnd 1,2 rsvd 1,2 + 5 v agnd/ dgnd vcc v cc
le5711 ve580 series data sheet 15 application circuit r ing_source r r2 400 ? r r1 400 ? r sr3 1.82 m ? r sr4 2 m ? c rt2 47 nf r sr1 1.82 m ? r sr2 2 m ? c rt1 47 nf rs 1 db 1 db 2 rs 2 hp 1 b 1 (ring) tmg 1 vbat tmg 2 db 2 dac b 2 (ring) a 1 (tip) cdc 1 det 1 c1 1 c2 1 iref cas cdc 2 det 2 c1 2 c2 2 c ax1 r tmg1 r tmg2 bat d vbh db 2 c dc1 r ref c cas c dc2 ch1 ch2 22 nf ring 1 22 nf c bx1 bat 22 nf tip 2 ring 2 22 nf c bx2 bat dac r f1a 50 ? rr1 1/2 u2 c p 100 nf rr1 r f1b rs 1 2.49 k ? 2.49 k ? c ax2 r f2a 50 ? rr2 r f2b rs 2 c p 100 nf hp 2 a 2 (tip) 1.5 f 15 k ? 330 nf u1 le5711 rr1 u3 tip 1 rr2 det 1 c1 1 c2 1 det 2 c1 2 c2 2 r lac = 600 ? i loop = 30 ma bat = - 52 v digital ground battery ground analog ground 50 ? 50 ? 1.5 f bgnd 1,2 rsvd 1,2 + 5 v agnd/ dgnd vcc v cc 124 k ? db 1 db 1 r th1 1 m ? c th 100 nf r th2 909 k ? dac q 1 v bat shared between 4 dslic packages 20 m ? r dac vtx 1 rsn 1 r t1 r rx1 83.3 k ? vtx 1 c tx1 0.01 f vrx 1 c rsn1 0.1 f vtx 2 rsn 2 r t1 r rx1 83.3 k ? vtx 2 c tx2 0.01 f vrx 2 c rsn2 0.1 f 124 k ? 1/2 u2 c hp2 100 nf r hp2 15 k ? c hp1 100 nf r hp1 15 k ?
16 le5711 ve580 series data sheet line card parts list the following list defines the parts and part values required to meet target specification limits for channel i of the line car d (i = 1,2). note: 1. * shared between four dualslic device packages 2. refer to the thermal management for the le5711 and le5712 dual devices application note for particular conditions. item quantity type value tol. rating comments note c ax1 , c bx1 , c ax2 , c bx2 4 capacitor (x7r) 22 nf 20% 100 v c hp1 , c hp2 , c p 3 capacitor (x7r) 100 nf 20% 100 v c th capacitor (x7r) 100 nf 20% 50 v 1 c rt1 , c rt2 2 capacitor (x7r) 47 nf 20% 50 v c dc1 , c dc2 2 capacitor (x7r) 1.5 f 20% 5 v c tx1 , c tx2 2 capacitor (x7r) 0.01 f 20% 5 v c rsn1 , c rsn2 2 capacitor (x7r) 0.1 f 20% 5 v r f1a , r f1b, r f2a , r f2b 2 ptc or fusible 50 ? r ref 1 smt 15 k ? 1% 1/10 w r t1 , r t2 2 smt 83.3 k ? 1% 1/10 w r rx1 , r rx2 2 smt 124 k ? 1% 1/10 w r hp1 , r hp2 2 smt 15 k ? 1% 1/10 w d vbh 1 murs 120 (d0-41) diode r r1 , r r2 2 smt 400 ? 5 ? 1w u2 1 tisp6ntp2a r sr2 , r sr4 2smt 2 m ? 1% 1/10 w r sr1 , r sr3 2 smt 1.82 m ? 1% 1/10 w u1 1 le5711 device r tmg1 r tmg2 2 smt 1.8 k ? 5% 1 w 2 c cas 1 capacitor (x7r) 330 nf 20% 100 v r th1 *smt 1 m ? 1% 1/10 w r th2 * smt 909 k ? 1% 1/10 w r dac *smt 20 m ? 5% 1/10 w q 1 * npn bc639 50 v
le5711 ve580 series data sheet 17 physical dimensions 32-pin plcc note: packages may have mold tooling markings on the surface. these ma rkings have no impact on the form, fit or function of the device. markings will vary with the mold tool used in manufacturing.
18 le5711 ve580 series data sheet 44-pin etqfp note: packages may have mold tooling markings on the surface. these ma rkings have no impact on the form, fit or function of the device. markings will vary with the mold tool used in manufacturing.
le5711 ve580 series data sheet 19 revision history revision a1 to b1 ? added green package opns to ordering information , on page 1 ? added package assembly , on page 6 revision b1 to c1 ? removed non-green opns from ordering information , on page 1 . ? removed le57d113jc and le57d113djc from ordering information , on page 1 . revision c1 to d1 ? removed le57d113btc from ordering information , on page 1 .
20 le5711 ve580 series data sheet the contents of this document are provided in connection with legerity, inc. products. legerity makes no representations or war ranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time with out notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. except as set forth in legerity's standard te rms and conditions of sale, legerity assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. legerity's products are not designed, intend ed, authorized or warranted for use as co mponents in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of legerity's product could create a situation where personal injury, death, or severe property or environmental damage may occur. legerity reserves the right to discontinue or make changes to its products at any time without notice. ? 2006 legerity, inc. all rights reserved. trademarks legerity, the legerity logo and combinations thereof are register ed trademarks, and batterydirec t, islic, islac, phoneport, qls lac, voiceedge, voicepath, voiceport, the "v" in vo ip and winslac are trademarks of legerity, inc. other product names and marks used within this document are fo r identification purposes only and may be registered trademarks o r trademarks of their respective companies.
4509 freidrich lane austin, texas 78744-1812 telephone: (512) 228-5400 fax: (512) 228-5508 north america toll free: (800) 432-4009 to find the legerity sales office nearest you, or to download other documentation, go to: http://www.legerity.com for all other technical inquiries, please contact legerity tech support at: techsupport@legerity.com or call +1 512.228.5400. ?

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